Recent demand for lighter and thinner high-performance electronic devices has led to electronic devices with higher density integration and higher density packaging, and the semiconductor packages used in such electronic devices are becoming ever smaller than in the past.
Because of the limited ability to reduce the size of semiconductor packages that have a configuration employing conventional lead frames, area mounted types of semiconductor packages such as ball grid arrays (BGA) and chip scale packages (CSP) comprising semiconductor elements mounted on circuit boards have recently been proposed. In these semiconductor packages, known ways to connect semiconductor elements mounted on BGA to circuit boards include wire bonding, TAB (tape automated bonding), and flip-chip (FC) methods, but an abundance of BGA or CSP structures employing flip-chip connecting methods useful for the miniaturization of semiconductor packages have recently been proposed.
The flip-chip connecting method of mounting is thought to be more advantageous than wire bonding methods because less area is needed for mounting. Flip-chip, mounting is also characterized by good electrical properties because the circuit wiring is shorter. Flip-chip mounting is an excellent connecting method for the circuits of portable devices which, due to strong demand, need to be made smaller and thinner, high frequency circuits which are highly regarded for their electrical properties, and so forth.
In flip-chip mounting, interposers that have a core layer and a build-up layer are generally used to connect semiconductor elements. In the interposers, the need to handle even higher density packaging and to meet demand for faster operating frequencies has resulted in the proposal of a thin build-up interpose, wherein a smaller overall interposer thickness and a shorter interlayer connection length for handling higher frequencies are achieved by making a thinner core layer or by dispensing with the core layer altogether and using an interposer that is a laminate in which wiring patterns are formed in resin or the like (Patent Document 1, for example).
Vertical continuous connections in the build-up layers of the interposer, referred to as stacked via connections, are being adopted to handle ever higher frequency transmissions. Stacked vias comprise vias stacked up directly on top of each other in a plurality of stages, allowing the wiring distance to be shortened and thereby effectively reducing inductance (Patent Document 2, for example).
In flip chip-mounted semiconductor packages, the gaps between semiconductor elements and circuit boards are usually filled with a reinforcing resin composition (underfill) to ensure the reliability of the connections between semiconductor elements, circuit boards, and metal bumps, etc. Thermosetting resins such as epoxy resins have been widely used in the past as an underfill material.
In these semiconductor devices, the functioning surfaces of silicon chips are electrically connected to circuit boards through a conductive material oriented toward the circuit board side, and the gaps between the silicon chips and circuit boards are filled with a thermosetting resin composition that is then cured. The thermosetting resin compositions also have C10 to C30 linear aliphatic hydrocarbon compounds which chemically combine with the thermosetting resin. These have high temperature cycle reliability, yet allow silicon chips to be removed at low temperature and low shear force, without damaging the silicon chips or circuit boards (Patent Document 3, for example).
Patent Document 1: Japanese Patent Application Publication No. 2006-24842A
Patent Document 2: Japanese Patent Application Publication No. 2001-35960A
Patent Document 3: Japanese Patent Application Publication No. 11-233571A